Thermal/Traffic-aware 3D Network-on-Chip (NoC) Designs
Abstract: Three-dimensional Network-on-Chip (3D NoC), the combination of NoC and 3D IC technology, can achieve lower latency, lower power consumption, and higher data bandwidth for efficient intra/inter-chip data exchange of chip multiprocessors (CMPs). However, due to die stacking in 3D IC, both heat conduction path and power density increase. It has been shown that NoC operations have comparable thermal impact as processing units, and significantly contributes to overall chip temperature. Besides, busy routers are prone to be overheating hotspots, which lead to the vulnerability of performance and reliability of NoC. To ensure thermal safety while avoiding huge performance degradation from the temperature constraint, several new design methodologies based on smart routing schemes and proactive thermal management for thermal- /traffic-aware 3D NoC designs will be presented in this talk.
An-Yeu (Andy) Wu (IEEE M’96-SM’12-F’15) received the B.S. degree from National
Taiwan University in 1987, and the M.S. and Ph.D. degrees from the University of
Maryland, College Park in 1992 and 1995, respectively, all in Electrical Engineering.
From August 1995 to July 1996, he was a Member of Technical Staff (MTS) at AT&T Bell Laboratories, Murray Hill, NJ, working on high-speed transmission IC designs. From 1996 to July 2000, he was with the Electrical Engineering Department of National Central University, Taiwan. In August 2000, he joined the faculty of the Department of Electrical Engineering and the Graduate Institute of Electronics Engineering, National Taiwan University (NTU), where he is currently a Professor. His research interests include low-power/high-performance VLSI architectures for DSP and communication applications, adaptive/multirate signal processing, reconfigurable broadband access systems and architectures, bio-medical signal processing, and System-on-Chip (SoC)/Network-on-Chip (NoC) platform for software/hardware co-design. He has published more than 190 refereed journal and conference papers in above research areas, together with five book chapters and 16 granted US patents.
Dr. Wu is now serving an Associate Editor for JOURNAL of SIGNAL PROCESSING SYSTEMS (JSPS), and had served as Associate Editor for many leading IEEE journals in circuits and signal processing areas, such as the IEEE TRANSACTIONS ON SIGNAL PROCESSING, the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—PART I, the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—PART II, and the IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. He acted as the Lead Guest Editor of the special issue of “2010 IEEE Workshop on Signal Processing Systems (SiPS) in JSPS (published in Nov. 2011), and the special issue of “Signal Processing for Broadband Access Systems: Techniques and Implementations,” in EURASIP Journal on Applied Signal Processing (published in December 2003). He also acted as the Guest Editor of a special issue of “Low-Power, Reliable, and Secure Solutions for Realization of Internet of Things,” in IEEE Journal on Emerging and Selected Topics in Circuits and Systems (published in March 2013). He also served on the technical program committees of many major IEEE International Conferences, such as ISCAS, ICASSP, SiPS A-SSCC, AP-ASIC, SOCC, and ISPACS. Prof. Wu served as the General Co-Chair of 2013 International Symposium on VLSI Design, Automation& Test (VLSI-DAT), and 2013 IEEE Workshop on Signal Processing Systems (SiPS). He also served as Technical Program Co-Chair of 2014 International SoC Design Conference (ISOCC) and 2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS). From 2012 to 2014, he served as the Chair of VLSI Systems and Applications (VSA) Technical Committee (TC), one of the largest TCs in IEEE Circuits and Systems (CAS) Society.
From August 2007 to Dec. 2009, he was on leave from NTU and served as the Deputy General Director of SoC Technology Center (STC), Industrial Technology Research Institute (ITRI), Hsinchu, TAIWAN, supervising WiMAX, Parallel Core Architecture (PAC) VLIW DSP Processor, and Android-based Multicore SoC platform projects. From 2012 to 2013, Dr. Wu served as the Deputy Director of Graduate Institute of Electronics Engineering (GIEE) of National Taiwan University. Since March 2014, Dr. Wu is in charge of the overall talent cultivation program in National Program for Intelligent Electronics (NPIE), under sponsorship of Ministry of Education in Taiwan.
Dr. Wu received numerous awards for his technical achievements and academic society services, including 2010 Outstanding EE Professor Award from The Chinese Institute of Electrical Engineering (CIEE), Taiwan, two Best Paper Awards in 2014 and 2010 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Excellent Patent Award from Industrial Technology Research Institute (ITRI) in 2009, Teaching Award of Common Education Course, National Taiwan University in 2007, Dr. Wu Ta-you Award (Young Investigator Award) from National Science Council (NSC), Taiwan (the only nominee from Microelectronics research group of the NSC) in 2005, Distinguished Young Engineer Award from The Chinese Institute of Electrical Engineering (CIEE) in 2004, Best Engineering Paper Award, from the Chinese Institute of Engineers (CIE), Taiwan in 2004, and Young Chair Professor Award from Macronix International Corporation (MXIC) Education Foundation in 2003. In 2015, Prof. Wu is elevated to IEEE Fellow for his contributions to “DSP algorithms and VLSI designs for communication IC/SoC.”
Designs of high-frequency and high-efficiency amplifiers
-Applications of computation algorithm of bifurcation analyses to amplifier designs
High-frequency and high-efficiency power amplifiers have important
roles of many applications such as dc-ac inverter of resonant
amplifier, transmitter part of wireless power transfer, RF power
source, and so on. Soft switching techniques are necessary for
achieving high power conversion efficiency at high frequencies. It is,
however, not easy to design for satisfying the soft switching
By the way, switching converters are typical nonlinear systems with external force. Therefore, the power-electronics research filed is very familiar with nonlinear-system analysis research field. Actually, many instability analyses of power converters have been carried out by using analytical techniques developed by the nonlinear-system analysis research fields. In other words, switching converters are regarded as concrete objects of nonlinear-system analyses. It is my claim that nonlinear-system analysis techniques should be used not only instability analyses but also designs of power converters more actively.
This talk presents the principle operations of high-frequency and high-efficiency power amplifiers and the design method based on computation algorithm of bifurcation analyses. Design examples and measurement results are also shown.
Hiroo Sekiya received the B.E., M.E., and Ph. D. degrees in electrical
engineering from Keio University, Yokohama, Japan, in 1996, 1998, and
Since April 2001, he has been with Chiba University and now he is an Associate Professor at Graduate School of Advanced Integration Science, Chiba University, Chiba, Japan. From Feb. 2008 to Feb. 2010, he was with Electrical Engineering, Wright State University, Ohio, USA as a visitng scholar. His research interests include high-frequency high-efficiency tuned power amplifiers, resonant dc/dc power converters, dc/ac inverters, magnetic component designs, and digital signal processing for wireless communications.
Dr. Sekiya received 2008 Funai Information and Science Award for Young Scientist, 008 hiroshi Ando Memorial Young Engineering Award, and Erricson Young Scientist Award 2008. He served chairs of IEEE CASS NCAS-TC(2013) and PECAS TC(2014) and organizing committees of many international conferences.
He is a senior member of IEEE and IEICE, Japan.